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AD7606 - big spread code on dc histogram

Question asked by Lukasz_Brzyszkiewicz on Jun 29, 2017
Latest reply on Sep 3, 2017 by nirb81

Hello,

 

i have problem with AD7606. On my board I have two AD7606 with sampling 16-channels in same time. I use internal reference voltage. When I'm reading data from ADC (SPI at 21MHz, oversampling off) I have DC histogram like this (in 5 sec time window):

 

-3LSB = 16

-2LSB = 3'670

-1LSB = 80'610

0LSB = 267'492

+1LSB = 147'294

+2LSB = 13'050

+3LSB = 164

 

In data sheet on page 30, AD claims that with no oversampling maximal spread is -2 LSB to +3 LSB. If I scale my readings to total occurences from datasheet I have:

-3LSB = 0.064 (DataSheet = 0)

-2LSB = 14.67 (DataSheet = 3)

-1LSB = 322.25 (DataSheet = 131)

0LSB = 1'069.35 (DataSheet = 928)

+1LSB = 588.83 (DataSheet = 887)

+2LSB = 52.17 (DataSheet = 97)

+3LSB = 0.655 (DataSheet = 2)

 

I wonder if obtained accuracy is maximum from this ADC with internal VREF and with no oversampling or my board isn't good and I must modify it.

 

Can anyone help me with this matter?

 

I have tried so far:

1) change sampling ratio between 12.8kHz, 25.6kHz and 51.2kHz - same results

2) increase analog line filtering capacitor - same results

3) significantly reduced common mode noise - same results

4) added snubber on dc/dc converter - removed peaks but same results

5) added LC filter on dc/dc output - less noise but same results

6) removed L filter from ADC analog voltage - less analog voltage ripple but same results

 

so - I have no more idea what is wrong. It can be clock jitter ? but I measure shorted to ground inputs, so this is DC.

I have attached schematic of ADC with inputs and power source of ADC.

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