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Knowing latencies of interrupt from external peripheries on ADSP-SC58x

Question asked by Usaghi2nd on Jun 29, 2017
Latest reply on Jul 12, 2017 by PrasanthR


I would like to know how much cycles would be taken when interrupt came from external peripheries, for example PINT0 ?


I assume System Event Controller might take cycles but I could not find descriptions in HRM and PRM.

I only find following in regard to cycles in processor core in HRM and this EngineerZone as DOC-12405(What is the minimum latency between a Core interrupt and the branch to the IVT?), has to be add to the cycles consumed in SEC.



The processor responds to interrupts in three stages:

  1. Synchronization (1 cycle)

  2. Latching and recognition (1 cycle)

  3. Branching to the interrupt vector table (11 instruction cycles)


If the branch is taken from internal memory, the 11 instruction cycles corresponds to 11 core clock cycles. If the branch is taken from external memory, the 11 instruction cycles may span over many more clock cycles depending on the actual source of the instruction and the state and configuration of the system.



Your helps always be appreciated.


Best Regards,