8 Bit SPI interface to AD9361
We have designed a board using TI Keystone -2 DSP (TCI6638K2K) DSP and AD9361 RF IC. The SPI on DSP supports either 8 bit or 16 bit SPI data interface.
However since we need 24 bit SPI data interface on AD9361 , we have fragmented 24 bits into 3 byte transfer and is each byte is transferred individually on SPI bus.
GPIO CS pin low
GPIO CS pin high
I have attached the SPI waveforms. As you infer that the CLK is not continuous and is halted between each transfer. However the CLK and DATA is aligned for each byte transfer.
Is this okay for configuring and controlling the AD9361