Our FPGA team is facing the following problem:
It says that IP for JESD204B is design linked only
What is the meaning of this ?
We have The evaluation licence from Xilinx already installed in the system. We could generate bitstream for Xilinx reference design having JESD204B IP core
But somehow we are unable to generate bitstream for Analog Devices Reference Design. Kindly help us out with this
To save time, If a bit file is readily available, please share with me.