We are developing a project trying to interface the AD9371 to a Zynq Ultrascale+ ZU4EG.
All signals on the FMC connector are crystal clear except for FPGA_REF_CLK and FPGA_AUX_CLK.
When the AD9371 evaluation board is connected to the zc706 board these signals are connected to two different banks of GTX transceivers. In our MPSoC we only have one bank of GTH transceivers available (16 channels).
The question is, what is the difference between FPGA_REF_CLK and FPGA_AUX_CLK? Why are both required? I looked into the users guide and didn't find any hint.