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[ADV7511W] TMDS PLL Lock time.

Question asked by Tamu on Jun 27, 2017
Latest reply on Jun 29, 2017 by Tamu

Hello,

 

I have a question about ADV7511W.

This question is related to the following thread.
https://ez.analog.com/message/273486

 

In this thread, I asked the TMDS PLL lock time after the registers are set.
Mr. Mike commented as follows:

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> Incorrect frequency at output is due to PLL free running at startup until it achieves lock.
> As I said previously allow a settle time for the PLL to lock and video to stablise and it looks like

> the customer was doing this with a wait time of 110mS.
> ADV7511W is a older part, newer Tx's were designed in such a way that they have a defined power up sequence
> so that you will not seen spurious frequency on the TMDS outputs.
> The only way around this on ADV7511W is to implement a delay as customer has already done.

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> The designers expect the PLL lock time to be in the order of tens of milliseconds up to a couple of video frames.
> There is a gears and such that the PLLs can select in order to be in the correct lock/acquire range.
> All in all this process is expected to take only a few video frames at most.
> At 60Hz refresh that would be 16ms per video frame. So a wait time of 110ms is approx 6 video frames

> at a 60Hz refresh.
> Unless the input was of very bad quality (ie. jittery, bad signal integrity) then 110ms is seen by our designers

> as an ample
> time to wait to allow the PLL to lock under normal circumstances.

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Please see the thread:
https://ez.analog.com/message/273486

 

Question:
 Could you guarantee below 110ms until the TMDS PLL achieves lock from setting the registers appropriately?
 If 110ms is too short, a little longer time is OK (for example, 200ms etc.).

 

Background:
 As the customer implemented their S/W including the wait time, they want your guarantee.

 

Thank you!
Best regards.

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