As we do not require deterministic latency for our application (spectrum analyzer), we are planning to set-up the JESD204B interface between the ADC and FPGA in sub-class 0 mode. We use Xilinx Kintex ultrascale FPGA for base-band processing. Also, the ADC configuration/sampling rate is such that, the lane rates can be as high as 12.5 Gbps
Although, the data sheet of the ADCs and Xilinx JESD IP core say that sub-class 0 mode is supported, I would like to confirm the following :
1) Does operating the JESD204B in sub-class 0 mode have any side effects that we should be aware of ?
2) Does it affect the lane rate in any way ?
3) Can I leave the SYSREF pins floating if I only need sub-class 0 operation ? (the data sheet says so)
4) Since AD6688/AD9208 have dual ADC cores, does not having SYSREF cause any issues in the alignment of samples between these two ADC cores on the Rx side (FPGA) ?