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Setting Clock Frequency on AD9528

Question asked by trushed on Jun 26, 2017
Latest reply on Jul 10, 2017 by trushed



I am currently trying to configure the AD9528 clock gen chip for use with the AD9371 transceiver.  I would like to set the OUT1 frequency to 240 MHz.  To do so I decided on the following divider values:

  • M1 = 4
  • N2 = 125
  • R1 = 16
  • chDIV = 4



  • Therefore the VCOfreq = (VCXOfreq*M1*N2)/R1 = (122.88 MHz * 4 * 125)/16 = 3840 MHz
    • Which is in the allowable VCO range for VCO (3450 MHz to 4025 MHz)
  • And my ClkFreq = VCOfreq / (M1*chDiv) = 3840 MHz /(4 * 4) = 240 MHz
    • My desired value

However, when trying to run this, the PLL did not lock.  I believe this is due to the fact that the PLL2 feedback divider paths (normal path and VCO Cal path) are not equal.  Basically, I want VCO CAL divider = 500, which is M1*N2.  But it does not look like I can configure the VCO Cal Path with a divider that large.  It looks like the VCO Cal divider is limited to the following:

  • VCO CAL divider = 4*B+A
    • where B is a maximum of 63 and A is a maximum of 3
    • This results in a maximum divider for the VCO Cal divider of 255

I am confused how N2 and M1 would have acceptable values that are inconsistent with the other feedback paths.  Can you please advise me on a workable path to get 240 MHz clock frequency with consistent feedback dividers in PLL2?