Could you please let me know if on using external clock and disabling SPLL without using internal HF Internal OSC can i save more power .
Or is it the same on using internal clock .
With best regards and wishes
What do you exactly mean by external clock? I believe you are talking about the GPIO P1.10 in SYS_CLKIN mode. In case you are referring to the external crystal, definitively, this will be more power hungry than using the HFOSC.
Here do you have a few clarifications:
In general, our recommendation is to use the internal HFOSC and enable the DCDC.
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