Which part of the document will explain this?
The diagram shows that LRCLK can be high or low.
The default is for the LRCLK to go low at the start of the frame for I2S. So the false define would do this. It would make the left channel be low.
The only complication is for TDM mode. When in TDM mode and with the LRCLK in Pulse Mode, the LRCLK should be inverted so the pulse is a short positive pulse. Some newer parts will automatically do this so that is where it becomes confusing.
What part are you using? The procedure differs slightly across parts.
Thank you very much.
But maybe my question is not clearly.
for example .ad1979 or ad1962a, the demo code shows below.
#ifdef TDM_MODE#define LRCLK_HI_LO_1979 (false)#else#define LRCLK_HI_LO_1979 (true)
Is the true or false can be see from the timing diagram?
I think this problem is already solved.
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