I am working with a PicoZed SDR AD9361 Development Kit. I've added some HDL blocks which, on their own simulate and synthesize just fine. I get the following error when I run make:
ERROR: Timing Constraints NOT met!
I get around the problem by running the [generated] Vivado GUI and simply selecting the synthesis option: "Flow_PerfOptimized_High". This allows the project to be implemented with no timing errors.
I imagine that I should be able to achieve the same functionality if I insert the following command in the right place in the right tcl file:
set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1]
So which is the right tcl file and where should it be inserted? I've tried a variety of tcl files and this command is always ignored.
(BTW, I always run a "make clean" before running the regular "make").
Any help would be greatly appreciated.