I built the reference design for AD-FMCJESDADC1 FMC Board with Xilinx KC705.
Xilinx Vivado 2015.4.2 (as required by the latest release)
Cygwin with make and git package
When I executed make command, it didn't give me error message but it also didn't seem to finish. I opened the project file and it seemed ok.
The synthesis was successful but it failed timing during implementation.
I didn't change any of the code so I don't know why it failed timing.
Can anyone tell me how to fix this?