AnsweredAssumed Answered

Reference Design TNS Violation

Question asked by SylviaF on Jun 23, 2017
Latest reply on Jun 27, 2017 by SylviaF



I built the reference design for AD-FMCJESDADC1 FMC Board with Xilinx KC705.

My setup:

Xilinx Vivado 2015.4.2 (as required by the latest release)

hdl_2016_r1 (the latest release from

Cygwin with make and git package


When I executed make command, it didn't give me error message but it also didn't seem to finish. I opened the project file and it seemed ok.

The synthesis was successful but it failed timing during implementation.

I didn't change any of the code so I don't know why it failed timing.

Can anyone tell me how to fix this?


Thank you!