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HMC7043 Pulse LVDS Mode

Question asked by jnet on Jun 23, 2017
Latest reply on Jul 11, 2017 by kpeker

I am configuring some channels of the HMC7043 as follows:

driver mode - LVDS

Idle at zero mode - force to logic 0

startup mode - dynamic

enable  - on

enable sync - on


When I issue a pulsor request for these channels, the output looks strange.  It seems to have 3 states.  The state seems to default high, then when the pulsor request is issued, it transitions to a lower level, then the pulse itself has an even lower level.  


If I change the driver mode to LVPECL, I see a normal pulse (state defaults to high, and then transitions low for the duration of the pulse).


Can you provide any guidance as to what I might be happening here and what I might be doing incorrectly when using LVDS mode?  The output goes to an FPGA input.  We have a 100 ohm resistor in place between the differential output lines of the HMC7043.


Thank you in advance for any help you  can provide!