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AD9208 CLK+/CLK− , Sample Rate

Question asked by sss on Jun 23, 2017
Latest reply on Jul 6, 2017 by UmeshJ

Hi all,

 

In the datasheet, clock specification @ AD9208,

 Clock Rate (at CLK+/CLK− Pins) 3(typ) 6(max) GHz
 Sample Rate 2500(min) 3000(typ) 3100(max) MSPS
 The maximum sample rate is the clock rate after the divider.

 

This means @ full sample rate,
1.With using ÷1 clock divider, CLK+/CLK− pins direct input is 3100(max) MSPS = fsADC.
  It cannot input directly 6000(max) MSPS because of over fsADC 3100(max) MSPS .

2.With using ÷2 clock divider, CLK+/CLK− pins direct input is 6000(max) MSPS, fsADC = 6000/2 = 3000(max)MSPS.

 

Is it correct understanding?

 

Best regards,
sss

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