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Length Matching requirement for JESD204B

Question asked by vish1ram on Jun 23, 2017
Latest reply on Jun 29, 2017 by kpeker

Hi All,


I am working on AD9680 ADC, which is using JESD204B subclass 1 for data transfer. We made custom board which has AD9860 ADC and HMC7044 for clocking. In our setup receiver is Xilinx FPGA Board(zynq ultrascale+). 


I have few queries  for length matching requirements of ADCLK and SYSREF of devices.

1. is ADCCLK and SYSREF from HMC7044 to ADC9680 should be length matched? FPGA CORECLK and  SYSREF from HMC7044 Should be length matched?

3. is All the clocks (ADCCLK, ADC-SYSREF, FPGA CORECLK and FPGA-SYSREF) from HMC7044 should be length matched?


We have 4 ADC (AD9680) chips on our board. Is it required for length matching of all Clocks and SYSREF for synchronization?


Thanks & Regards

Rama Krishna