I defined LBW = 200 kHz, PD = 50', and CP current = 0.313 mA, and obtained the fast lock loop filter circuit from ADIsimPLL. The output spectrum is as shown in the attached picture, it seemed like the loop filter is unstable?
I have checked the component values from ADIsimPLL are same as those I am using on my design. Can somebody guide me what could be my mistake? I'm attaching the ADIsimPLL design file here as well.
When I compared my loop filter part values to other typical designs, the capacitor values are comparably much smaller. Could this cause the loop to be unstable?