I want to change the frequency of bbpll, I have a confirguration of bbpll = 983.04. it worked well
can i change the bbpll frequency to 864?
BBPLL frequency depends on signal path clocks.
"The BBPLL synthesizes an integer multiple of the Rx ADC clock, the Tx DAC clock, all analog calibration clocks, as well as the clocks used in the digital section. The BBPLL operates of the range of 715 MHz to 1.430 GHz, which allows practically any sample rate to be generated from any reference frequency. "
For more details refer UG-570 BBPLL section.
Why you want to change BBPLL independently?
ok, it means that the adc clock can be any value?
i changed BBPLL so i can change adc clock, my fpga cant run fast.
if i changed bbpll value, if i need to change the loop filter?
ADC clk and data path clk depends on the decimation set.
Please refer UG-570 filter section to understand better.
No need to change loop filter value.
We recommend to use ADI provided drivers.
Retrieving data ...