I am developing the interface between ad9642 and a xilinx fpga. And I need to understand the output timing of AD9642 in detail (especially the relation between DCO and Di). In datasheet it is only said that t_skew (DCO-to-Data Skew) is min 0.3 ns, typ 0.5 ns, max 0.7ns. Does it actually mean the timing as in the attachment?
E.g. for DCO 200 MHz, so T = 5 ns, rising edge data is guaranteed to be stable from 0.3 ns before the rising edge of DCO and until 0.7 ns before the falling edge of DCO; 2.1 ns stable, 0.4 ns uncertainty, correct?