I'm working on a design based off of the FMCDAQ2 with the ZC706. All I have changed is the device tree (for a new clock distribution configuration, nothing to do with the IP cores) and updated the constraints file in the Vivado 2016.2 project (new layout for pins). I'm using Linux 2016_R2 and hdl_2016_r2.
I get the following messages saying these devices are mapped:
cf_axi_adxcvr 44a50000.axi-ad9680-adxcvr: AXI-ADXCVR (16.01.a) at 0x44A50000 mapped to 0xf0976000,
cf_axi_adxcvr 44a60000.axi-ad9144-adxcvr: AXI-ADXCVR (16.01.a) at 0x44A60000 mapped to 0xf0978000,
cf_axi_jesd204b_v51 44a90000.axi-jesd204b-tx: AXI-JESD204B 7.0 Rev 1, at 0x44A90000 mapped to 0xf097a000,
cf_axi_jesd204b_v51 44a91000.axi-jesd204b-rx: AXI-JESD204B 7.0 Rev 1, at 0x44A91000 mapped to 0xf097c000,
cf_axi_dds 44a04000.axi-ad9144-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.00.b) at 0x44A04000 mapped to 0xf09b0000, probed DDS AD9144
cf_axi_adc 44a10000.axi-ad9680-hpc: ADI AIM (10.00.b) at 0x44A10000 mapped to 0xf09c0000, probed ADC AD9680 as MASTER
But I do get this error message:
cf_axi_adxcvr 44a60000.axi-ad9144-adxcvr: TX Error
When I check the axi-jesd204b-tx configuration parameters I get this for all the lane infos (and as well for rx):
DID: 0, BID: 0, LID: 0, L: 1, SCR: 0, F: 1
K: 1, M: 1, N: 1, CS: 0, S: 1, N': 1, HD: 0
FCHK: 0x0, CF: 0
ADJCNT: 0, PHYADJ: 0, ADJDIR: 0, JESDV: 0, SUBCLASS: 0
MFCNT : 0x0
I compared these with what shows up using the DAQ2 board and they do not match up.
Why could this be happening?