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AD9148 "Data Rate" Synchronization mode - datasheet bit definition errors

Question asked by bmd on Jun 21, 2017
Latest reply on Aug 8, 2017 by bmd

AD9148 "Data Rate" Synchronization mode - datasheet bit definition errors

 

Referencing the AD9148 Datasheet[1], the SPI register table and datasheet text are contradictory with regards to the proper register setting for selecting the "Data Rate" synchronization mode.

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Table 13, page 29, says bit 6 of Register 0x10 (Sync Control 0) is defined as follows:

  FIFO reset rate (0) / data rate (1)

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But all of the text in the datasheet (search datasheet for "Bit 6 of register 0x10") says the opposite, i.e.

  page 43: "The data rate synchronization is selected by setting Bit 6 of Register 0x10 to 0."

 

  page 44: "Data rate synchronization (default), Bit 6 of Register 0x10, is set to 0."

                  "FIFO rate synchronization, Bit 6 of Register 0x10, is set to 1."

etc.

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Which is the correct setting for Register 0x10, bit 6, to select "Data Rate" synchronization mode?

 

-Brian

 

[1] http://www.analog.com/media/en/technical-documentation/data-sheets/AD9148.pdf 

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