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ADV7403 Component Processor (CP) – 1.1uS video delay (20 pixels)

Question asked by Redders on Oct 13, 2011
Latest reply on Nov 10, 2011 by DaveD

I am using the ADV7403 Video Decoder in CP mode to digitise a CVBS video (luma only).

This allows the full bandwidth signal to be digitised in square pixel mode without the normal PAL filtering restrictions (6.25MHz).

 

I setup the EVAL-ADV 7401/3EBZ evaluation board with the following registers settings :-

 

0x05       Primary Mode                   01           Turn on Component mode.

0x06       Video Standard                 03           625i 4x2 (1440x576)

0x3C      TTLC Control                   53           Increase PLL Pump charge

0x87       CP TLLC Control 1          E7           Set PLL divider ratio

0x88       CP TLLC Control 2          60           Set PLL divider ratio

0x8A      CP TLLC Control 4          90           Enable manual VCO range

 

The composite input is on AIN1 and SOG. Note on-board clock is 28.636MHz.

 

This all works without any problems but…….

 

When I set this up on my PCB design I get a 1.1us delay at the start of active video.

delay_waveform.jpg

My board clock is 27MHz, but I have changed this to 28.636MHz and set register  0x1D to 0x47 to enable 28MHz.

My CVBS video is input to AIN1 & SOG.

 

My register setting are (Register Address, Write value) :-

 

C3 F1 ;                   ADC0_SW = AIN1

C4 FF ;                   SOG select

05 01 ;                   Prim_Mode =001b for Component mode

06 03 ;                   VID_STD=0011b for SD 4x1 625i (1440x576)

1D 07 ;                   Disable 28MHz Crystal 27MHz

3B 80 ;                   Enable External Bias

3C 53 ;                   PLL_QPUMP to 011b

6B C3 ;                   Select 422 8 bit YPrPb out from CP

7B 0A ;                  clears the bits CP_DUP_AV and AV_Blank_EN

85 19 ;                   Turn off SSPD and force SOY. For Eval Board,Enable DS_Out

86 0B ;                   Enable stdi_line_count_mode

C5 01 ;                   CP_CLAMP_AVG_FACTOR[1-0] = 00b

C9 0C ;                   Enable DDR Mode

F3 07 ;                   Enable Anti Alias Filters on ADC 0,1,2

67 00 ;                   DPP_FILT CHB Decimation x4, DS_ONLY on

68 00 ;                   DPP_AFILT Manual select

7B 0A ;                  CP AC Control - AV Blank, AV Code EN

87 E7 ;                   Set PLL Divider ratio

88 60 ;                   Set PLL Divider ratio

8A 90 ;                   Enable Manual VCO Range

67 00 ;                   DPP_FILT CHB Decimation x4, DS_ONLY on

68 00 ;                   DPP_AFILT Manual select

 

I would appreciate any help on this as the ADV7403 is a complicated device and I am losing hair.

 

Peter Redmond

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