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AD6676 Configuration

Question asked by Pbergada on Jun 21, 2017
Latest reply on Aug 24, 2017 by PMH


we are bringing up a board with one HMC7044 and one AD6676. Our goal is to set up a JESD204B/subclass 1 link between AD6676 and a JESD204B receiver placed in a FPGA. We have configured HMC7044 to generate the clock and the SYSREF signal to both the ADC and the JESD204B receiver. 


The clock to the ADC is 3.19488 GHz and the clock to the transceivers and core of JESD204B receiver is 133.12 MHz (ADC_clock/24). SYSREF signal is a one-shot pulse which is phase synchronized with DCLK outputs of HMC7044.

As you can see in the couple of plots below (the second one is a zoom in of the first one), the receiver deasserts the RX_SYNC signal once the SYSREF signal reaches the receiver. It then asserts rx_tvalid and outputs the start/end of frame/multiframe, which seems to be correct (please find attached the ADD6676 configuration). The problem here is that the I and Q output bus shows something similar to noise (at almost full scale) when we connect a 365 MHz signal from a generator to the input of the ADC (ADC_NCO=370 MHz).


The frame error bus, at receiver, doesn't  show any error and the RX transceivers are both in lock state (we are working with 2 lanes as IQ rate is 266.24 Msps). The JESD204B receiver is configured as:

  • LMFC buffer size: 256
  • Lanes per link: 2
  • Sample SYSREF on: Negative edge
  • Default SYSREF: SYSREF always on
  • Scrambling off
  • F:2
  • K:32
  • SYSREF no required on re-sync
  • Lane rate: 5.3248 Gbps
  •  Reference clock: 133.12 MHz
  • PLL type: CPLL 


We can't see whether the problem is AD6676 configuration, although it seems to be equal to JESD204B receiver, or it is physical problem of the link. Any help that my shed some light on this issue will be appreciated.


Thank you very much,



JESD204B link

JESD204B link