I'm planning to use an ADF4351 to generate clocks across its entire frequency range (35 Mhz - 4.4 Ghz). The part needs to generate a fast serial clock for a SERDES block on an ASIC and a divided version of the same clock for transceivers on an FPGA.
I had a few questions:
1) When using the EVAL-ADF4351EB1Z board, low output frequencies (below 400 Mhz) have an odd looking waveform when probed (into 50Ohm). A scope capture is attached. What is the reason for this and how can it be fixed? What is an ideal output network for wideband usage?
2) The 3rd harmonic of the RF output is significant, but it is desirable to have faster rise and fall times. Do you have a recommendation for a clock buffer IC? I was looking at the ADCLK905 as an option.
3) It is desirable to have control of the duty cycle of the clock output. Could this be done by connecting the VT input of the ADCLK905 to a DC voltage from a digipot?
For this application and set of requirements is there an IC that is more appropriate?
I've found the answers to these questions from experimentation.
1) This has to do with the output matching network. For low frequencies, the shunt inductor to VCCO should be larger around 100-200nH. As recommended in the datasheet, a 50 ohm resistor to VCCO should be used for wideband operation at the expense of output power.
2) The ADCLK905 works well for this purpose, but its jitter performance suffers slightly if its input slew rate is slow. Using a fast comparator (ADCMP582) or limiting amplifier (ONET1181P) also works for this purpose, at the expense of smaller final output swing and more jitter.
3) The internal clamping diodes of the ADCLK905 aren't designed to clip the input waveform. To have duty cycle control, a comparator must be used with the VCO fundamental output from the ADF4351. The output of the comparator can then be non-symmetric so it should be DC coupled to any other IC in the signal path to avoid distortion.