I'm working with a FMCOMMS5 board connected to a ZC706 dev board.
I'm currently working on my own HDL code that has doubled the number of data channels coming from digitizers, and I'm trying to now pipe that data to my dma (Same kind of DMA that is in used in the original HDL code, the ADI IP one). I want to use the util_cpack that ADI provides, but increasing the NUM_OF_CHANNELS parameter only increases the output size (Not ADIs fault, I know Verilog doesn't lend itself to array input/output very well). My question is, what do you think would be the best route to go for my application? Like I said, I've simply doubled the number of output channels coming from the digitizer/fifo. I also would like to stick with ADIs data format because, while I have developed my own Linux driver, I also use ADIs linux DMA driver implementation.
I've gone through and doubled the inputs on the util_cpack (it now goes from adc_data_0 to adc_data_15), but I'm not sure how to double the mux and dsf modules. I'll continuing to work on it and try to double everything, but I figured I'd ask you guys before I got too deep. I would also like the solution to be somewhat scalable, as I may want to quadruple the number of data channels.
I feel like there is an easier way that I'm missing.