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(ADV7480)When will ADV7480 moves to LP mode?

Question asked by donadona999s on Jun 20, 2017
Latest reply on Jun 20, 2017 by donadona999s

Hi !

 

 

I have a question about ADV7480.

(ADV7480)MIPI Power Up Sequence 

 

Q1)

When we use power up sequence, when does ADV7480 moves to LP mode?

And when does ADV7480 move to HS mode from LP mode?

 

1. Configure the number of active lanes using the num_lanes[2:0] control.
2. Enable the automatically computed DPHY timing parameters using en_autocalc_dphy_params,

    and configure any other miscellaneous MIPI CSI-2 Tx/DPHY parameters

    (as performed in the ADI recommended scripts).
3. Power up the MIPI DPHY using the dphy_pwdn control.
4. Set register 0x31[1:0] in the CSI Tx map to 0b10.
5. Set register 0x1E[6:5] in the CSI Tx map to 0b10.
6. Enable the MIPI CSI-2 Tx PLL using the mipi_pll_en control.

7. Wait for 1250 us, and then enable the MIPI CSI-2 Tx using the csitx_pwrdn control.
8. Wait for at least 350ns, then set register 0xC1[4] in the CSI TX map to 0b0
     Note: If the lane swap function is used to change the mapping of the MIPI lanes, then bit[4] of the

               register in the CSI TX map associated with the lane corresponding to the clock must be cleared as follows:
     • Register 0xC1[4] is set to 0b0 if the clock lane is output on CLKAP, CLKAN
     • Register 0xC4[4] is set to 0b0 if the clock lane is output on DA0P, DA0N
     • Register 0xC7[4] is set to 0b0 if the clock lane is output on DA1P, DA1N
     • Register 0xCA[4] is set to 0b0 if the clock lane is output on DA2P, DA2N
     • Register 0xCD[4] is set to 0b0 if the clock lane is output on DA3P, DA3N
     Up to this step, bit[4] of this register is to be kept set.
9. Wait for at least 100 ns, then set register 0x31[1:0] in the CSI TX map to 0b00.

 

 

Best regards

Kawa

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