Hello - has anybody used this setup and can help with configuration? I am trying to configure the AD9517-3 such that the LVPECL outputs are at 250MHz. The input ref on the FMC110 per their spec is 100MHz. I am unable to get the PLL to lock. I am setting the following AD9517-3 registers:
0x1C: 0x2 - use REF1 (100MHz)
0x11: 0xA - R divider 10 - get ref to 1000MHz
0x190: 0x33 - Divider 0 (3+1) cycles high, (3+1) cycles low to divide by 4 to get 250MHz
0x10: 0x7E - PLL Normal Operation
Read 0x1F - always get 0xE - PLL not locked
What am I doing wrong?
Thanks very much!