I have a question about an error in ADIsimPLL.
I'm now designing an integer-N PLL to synthesize 50 MHz to 800 MHz.
Simply, when I use internal prescaler, I should set division ratio to 16.
However, when I try to use ADF4106 in ADIsimPLL, following message appears.
ADF4106 is incompatible with these requirements:
P=8 Prescaler cannot achieve N value of 16
P=16 Prescaler cannot achieve N value of 16
P=32 Prescaler cannot achieve N value of 16
P=64 Prescaler cannot achieve N value of 16
No valid prescaler option could be found.
I cannot understand this message, because I think division ratio of 16 is possible according to datasheet of the ADF4106. (For example, just use only 6-bit A counter, 010000)
Is there any misunderstanding...?