Hello !

I have a question about an error in ADIsimPLL.

I'm now designing an integer-N PLL to synthesize 50 MHz to 800 MHz.

Simply, when I use internal prescaler, I should set division ratio to 16.

However, when I try to use ADF4106 in ADIsimPLL, following message appears.

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ADF4106 is incompatible with these requirements:

P=8 Prescaler cannot achieve N value of 16

P=16 Prescaler cannot achieve N value of 16

P=32 Prescaler cannot achieve N value of 16

P=64 Prescaler cannot achieve N value of 16

No valid prescaler option could be found.

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I cannot understand this message, because I think division ratio of 16 is possible according to datasheet of the ADF4106. (For example, just use only 6-bit A counter, 010000)

Is there any misunderstanding...?

Hello ,

Please see attached short presentation explaining why the min N value is P^2 - P, therefore if P = 16, the minimum value of N = 240, in order to be able to increment by N. In order to use an N value of 16, you should use P = 4.

See the datasheet on page 10...

PRESCALER (P/P +1)

The dual-modulus prescaler (P/P + 1), along with the A counter

and B counter, enables the large division ratio, N, to be realized

(N = BP + A). The dual-modulus prescaler, operating at CML

levels, takes the clock from the RF input stage and divides it

down to a manageable frequency for the CMOS A counter and

B counter. The prescaler is programmable. It can be set in software

to 8/9, 16/17, 32/33, or 64/65. It is based on a synchronous

4/5 core. There is a minimum divide ratio possible for fully

contiguous output frequencies. This minimum is determined by

P, the prescaler value, and is given by (P2 − P).

Regards,

Brigid.