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Pin assertion-to-state delays.

Question asked by dmitriy00 on Jun 16, 2017
Latest reply on Jun 22, 2017 by sripad

Does anyone know what the delay is, if any, between the assertion of TXNRX and ENABLE lines and transmitting or receiving IQ data? In other words, is there a delay between the pin assertion and the circuit ready for a specific state?

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