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AD9265-FMC-125EBZ SPI Control

Question asked by marcomercuri on Jun 16, 2017
Latest reply on Sep 27, 2017 by PMH

Dear all,

 

I started interfacing the AD9265-FMC-125EBZ. I read the AD9265 datasheet and I understood that I can control the ADC using either the "SPI mode" or the "External Pin Mode".

 

Looking at the AD9265-FMC-125EBZ, it seems that some Mode Selection (Table 15 AD9265 datasheet) are set phisically connecting the OEB, PDWN, LVDS, LVDS_RS, and DITHER pins to AGND. I guess this correspond to the "External Pin Mode". The SCLK/DFS, SDIO/DCS, and CSB pins are left floating to be controlled by the FPGA.

 

I understood that in "External Pin Mode", I have to set CSB to AVDD, and give proper voltage to SCLK/DFS and SDIO/DCS, depending on the modality I want to operate.

 

It is not clear to me how I can fully operate in "SPI mode". To use the SPI I should indeed set low the CSB and follow the timing diagram. However, after I set the registers, CSB goes high so I guess I enter again in "External Pin Mode". Since the eval board has some pins connected to AGND (OEB, PDWN, LVDS, LVDS_RS, and DITHER), I'm wondering if I lose all the setting I do with the SPI.

 

For example, let's imagine that through SPI I control OEB, PDWN, LVDS, LVDS_RS, and DITHER. After that, CSB goes to high. I believe I lose my setting since OEB, PDWN, LVDS, LVDS_RS, and DITHER are phisically connected to AGND. Also can I use the SPI if those pins are connected to a potential?

 

Can you please clarify this point? How can I operate fully in "SPI mode" or in "External Pin Mode"? Can I use both modes?

 

Thank you very much.

 

Best Regards,

Marco

 

https://wiki.analog.com/_media/resources/fpga/xilinx/fmc/ad9265_fmc_schematic_02_a03421b.pdf 

 

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