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ADRV9371-W/PCBZ HDL Reference Design: Timing Errors

Question asked by steview on Jun 16, 2017
Latest reply on Jun 27, 2017 by steview

We wish to develop applications from the reference design as a baseline.

 

Running through the 2016_r2 reference design for the AD9371 on the ZC706 platform

I have downloaded the latest version, and installed Vivado 2016.2 as recommended. I have used the Xilinx make as we run in windows. It seems to run through ok. It seemed to hang from the DOS prompt so I opened up the Vivado GUI. The project seems to have been made ok but failed synthesis.

When I continue to run from the GUI it does go through synth and impl - but fails timing worst case about -2 ns.

 

Is this correct?

Is there an archived Vivado project we could start from?

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