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ADuC7024 I2C Master block read more than 8 bytes

Question asked by luka234 on Oct 12, 2011
Latest reply on Oct 14, 2011 by MikeL

I am trying to implement I2C Master driver. I want to optimize data transfer with attached slave so I want to read data chunks larger than 8 bytes.


In AN 895 is described that it is possible but pdf and companion code are describing (and solving) problem differently. Pdf suggests that internal counter can be reloaded by writing to I2CxADR (I presume that internal counter will be updated to current value of I2CxCNT reg).


However AN 895 companion code (rev 0.2, February 2007, src I2C_Master7020.c) has implementation without using ADR for reload. Overall implementation looks like never been tested (I am sorry if I am wrong).


For example:


rxDat[ucRxCount++] = I2C1MRX;

if ((ucRxCount == 7 ) && (ucI2CNT = 1))

{ .....


is that a typo or a bad programming?


If it is a typo

     - than I see no way that that line ever be true because both counters increments with the same rate (check in the code)

if it is a bad programming

     - than it will be executed on ucRxCount == 7 but rest of the code does not have any sense


I unsuccessfully tried to understand intended logic behind updating CNT reg with provided look up tables (szI2C1CNT[] and szI2C1VAL[]).




- Is there more updated version of AN 895?

- What is proper logic to read more that 8 bytes?

- At what point is safe to update internal counter?

          I2C Rx is double buffer so there is big difference in

                    a) internal counter is updated on byte received and stored in buffer

                    b) internal counter is updated on byte read from MRX reg

                    c) ...