I am a FPGA newbie.
I am planning to write an s/w abstraction layer for different chips supporting JESD. As of now I am using latest HDL design which supports AD9371 and I would like to use same ( if possible) for other chips supporting JESD.
One obvious design difference will be different number of Tx /Rx/Orx channels.Considering I can manage this with existing design, what will be other chip specific dependencies in latest HDL design which will stop me using same design for different chips and may be future analog chip?
What will change in HDL design which is chip specific,considering they all use same JESD standard interface?