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FIFO underflow/overflow

Question asked by Sinill57 on Jun 15, 2017
Latest reply on Jun 16, 2017 by larsc



Can you please give me some more information on how underflow and overflow mechanics work in fmcomms2 reference design?

How do dac/adc FIFO cores react to this signal? Is it necessary that it passes through them before getting into ad9361 core?  What happens in ad9361 core when it receives underflows and overflows? Apart from setting registers to 1, does it stop producing valid signals to adc cores when overflow is detected or what it transmits to LVDS bus when underflow is detected?

Best regards,