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21371 packed i2s mode - channel 'swapping'

Question asked by esfld on Oct 11, 2011
Latest reply on Nov 22, 2011 by jeyanthi.jegadeesan



I have connected two sharc 21371s via packed i2s mode; 8 channels for each frame sync period.  Each sharc is both transmitting and receiving an i8s line to/from the other sharc, via DMA chaining on SPI5 (xmit) and 6 (rcv).  The frame sync and clock signals are externally generated and shared by both sharcs.


What I have below works, except for the fact that the data that ends up in TDM_RX_BUFB is not always properly aligned.  It's acting as if sometimes the DMA chaining begins on the rising edge of the frame sync input, and other times on the falling edge.  But I don't know why/how this could be.  Is there some mistake in the following code that could cause this type of problem?


.segment/dm  seg_dmda;


//define TCBs

.var     TCB_TX5A[4] = 0, 8, 1, TDM_TX_BUFB;
.global     TCB_TX5A;
.var      TCB_RX6A[4] = 0, 8, 1, TDM_RX_BUFB;
.global     TCB_RX6A;

//define receive and transmit buffers

.global    TDM_RX_BUFB; 
.var    TDM_RX_BUFB[8]=0,0,0,0,0,0,0,0;  /*Input buffer array*/

.global    TDM_TX_BUFB;
//try some fake data... is it working?
.var    TDM_TX_BUFB[8]=0x11111111,0x22222222,0x33333333,0x44444444,0x55555555, 0x66666666, 0x77777777, 0x88888888;


.segment/pm     seg_pmco;


//clear control regs

     r0 = 0x00000000;
       dm(SPCTL5) = r0;
    dm(SPCTL6) = r0;
      dm(SPMCTL5) = r0;
    dm(SPMCTL6) = r0;


//set up count regs

ustat3 = 8;
dm(CSP5A) = ustat3;
dm(CSP6A) = ustat3;


//set up modifier regs

ustat3 = 1;
dm(IMSP5A) = ustat3;
dm(IMSP6A) = ustat3;


//set addressing

ustat3 = TDM_RX_BUFB; dm(IISP6A) = ustat3;
ustat3 = TDM_TX_BUFB; dm(IISP5A) = ustat3;


//set up sports

r0 = SPTRAN |  //transmit mode
  BHD |     //buffer hang disable (debugging)
  SDEN_A |  //enable DMA on A
  SCHEN_A | //enable DMA chaining
  SLEN32 |

dm(SPCTL5) = r0;



r0 = BHD |     //buffer hang disable (debugging)
  SDEN_A |  //enable DMA on A
  SCHEN_A | //enable DMA chaining

  SLEN32 |

dm(SPCTL6) = r0;



r0 = NCH7 | MCEA;//need to set to num chans - 1
dm(SPMCTL5) = r0;
dm(SPMCTL6) = r0;//don't forget to enable multichannel mode


r0 = 0xff;//enable first 8 channels bit positions
dm(SP5CS0) = r0;
dm(SP6CS0) = r0;


//point the TCB to itself

r0 = (TCB_TX5A+3) & 0x7ffff; dm(TCB_TX5A) = r0;
r0 = (TCB_RX6A+3) & 0x7ffff; dm(TCB_RX6A) = r0;

//finally, load chain pointer regs to initiate

r0 = (TCB_TX5A+3) & 0x7ffff; dm(CPSP5A) = r0;
r0 = (TCB_RX6A+3) & 0x7ffff; dm(CPSP6A) = r0;    // here




It seems to me, that with both dsps set up as above,  they should each always have 0x11111111, 0x22222222, ......0x88888888 in their respective TDM_RX_BUFB buffers.  While this is sometimes the case, other times perhaps the first four slots will be full of zeros, while the last four have 0x11111111 - 0x44444444, and I have also seen the first four slots filled with the last four test words, and the last four filled with zeros.  So when the 'swapping' occurs, the other four slots are zero, which doesn't seem to make any sense.


I'm sure I'm overlooking something obvious but can someone point out what that could be?