I'm working with AD9361 fmcomms2 reference design and want to implement a constant delay (in data_clock periods) between the first sample pulled from dac DMA and the first sample pushed to adc DMA.
When I used just the iio_buffer_refill/push functions, this delay had significant variance, so I had to move to HDL modifications.
The first idea I implemented was to hack the DMA core a bit, making the up_sot register accessible from another custom core in HDL. This core simultaneously asserted the up_sot on both DMA's. This way, the delay variance was about +-5 samples.
I could either pass the mentioned signal from dac DMA to adc DMA for synchronization, with a start of transfer for adc DMA coming from PS, or have an ability to start a adc DMA transfer from PL. Any of them would do, but I don't know how to implement them.
There are fifo_wr_sync & fifo_rd_xfer_req signals that look like something I need, but there's very little documentation on them. Could you please tell me what they are used for and can they be used for my purpose?
And if not, how should I change the DMA cores to get such synchronization?