In RF I generate a signal between 1087 – 1093MHz
After downconversion it is with LO=1020MHz it is between 87Mz – 93MHz.
Assuming 200MHz ADC Clock Fs/2 is 100MHz.
Therefore the stop should be 77MHz and pass 93MHz.
However I did not know understand how to do with the decimating. ( is FS is reduced also by factor of decimation?).
If I have to get an output for 8Mega samples/sec how I should set the vaalues for Fpass and Fstop aand the overall(HB1*HB2*HB3*FIR) product?