Hi, I have AD9467-FMC with zedboard and I want to read IQ (I/Q) data using Vivado. Is there any reference design or some example or some suggestion that how one can do that. Many thanks
Have a look here: https://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467
Hi, The link you posted is just a HDL design and gives no indication how to do processing with I/Q samples and also no indication of how to using Xilinx tools such as Vivado and Xilinx system generator to incorporate I/Q samples to process using such tools. It would be great if Xilinx vivado and system generator designs are provided as they are much more flexible and doe not require knowledge of several other companies tools such as HDL.
Unfortunately we do not have them for this design.
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