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I2C0MSTA description in Table 127 in Rev.G of ADuC7026 datasheet

Question asked by KenW on Jun 13, 2017
Latest reply on Jun 14, 2017 by KenW

With reference to Table 127 in Rev.G of ADuC7026 datasheet, what is the difference between Bit 1 (Master transmit FIFO underflow) and Bit 0 (Master TX FIFO not full). Also, the Description of Bit 0 doesn't seem to be correct as it mentions "slave transmit FIFO" and "I2C0STX."

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