we are bringing up a board with an HMC7044, AD6676 and a FPGA to stablish a JESD204B link/subclass 1. We have succesfully programmed several outputs of HMC7044 as DCLK but we have a problem with SYSREF outputs. When we issue a pulse generator request from SPI, in SYSREF outputs appear several asynchronous pulses prior to the configured pulses (3 pulses in our case). Consequently the JESD204B receiver starts the protocol before expected and with pulses that are not synchronous to the reference clock. In fact it seems that the pulses are issued with a Reseed Request instead of a Pulse Generator Request (see attached code). Please, find below a plot of the SYSREF signal (IBUFDS_SYSREF_IBUF_OUT) along with several signals of the JESD204B receiver (JESD204B_rx_sync, JESD204B_rx_tvalid, ...) which can clarify the issue.
Sysref timer (0xC00) value is common multiple of all output dividers (0x10, 0x01, 0x600).
And attached we send you the SPI sequence to issue a Pulse Generator request.
Any light in this issue will be appreciated.
Thank you so much,