I am sing ADF4159 in my RF design. I want to realize a high speed FMCW ramp.
The time between each frequency hop is 0.1us = 100ns
Suppose the reference clock is 100Mhz, so fPFD is 100Mhz as well.
Is it possible to realize this fast ramp in ADF4159 in terms of chip itself, loop filter, bandwidth, and stability??
Anyone is welcome to answer this question!