All,

I am sing ADF4159 in my RF design. I want to realize a high speed FMCW ramp.

**The time between each frequency hop is 0.1us = 100ns**

Suppose the reference clock is 100Mhz, so fPFD is 100Mhz as well.

Is it possible to realize this fast ramp in ADF4159 in terms of chip itself, loop filter, bandwidth, and stability??

Anyone is welcome to answer this question!

The time between each frequency hop is defined by equation (8) in the datasheet:

Since both CLK1 and CLK2 are not allowed to be "1" the smallest hop time is 2*(1/Fpfd)= 20ns. Set the timer to 100ns with CLK1*CLK2=10. For example CLK1=1 and CLK2=10. The actual frequency deviation per hop is configured with Fdev (Equation 7) and the total number of hops stored in R6[22:3]. It is these values which determine the necessary loop BW and phase margin. Use ADISimPLL to check if the loop filter configuration will work for a given sweep requirement.