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Add custom IP for data generation FMCDAQ2

Question asked by xsun on Jun 12, 2017
Latest reply on Jul 13, 2017 by CsomI

Hello there,


I am modifying the HDL reference design for FMCDAQ2. I would like to add my custom IP, which is an encoder generating 64 bit encoded data, to the design. And also adding a decoder IP for decoding the received data.

Do you have an example for adding custom IP? I can only find one example for the fmcomms2:

Adding FIR filters in a fmcomms2 design [Analog Devices Wiki] 

I have also looked these pages:

ADI IP cores [Analog Devices Wiki] 

ADI Reference Designs HDL User Guide (Deprecated) [Analog Devices Wiki] 

From my understanding, if I used the custom IP as data source instead of dma, the upack/cpack and fifo ip can be replaced by my custom IP. The transmitted data can be connected directly to the ad9144_core as inputs(dac_ddata_x)? Which clock should I use for my IP? I suppose that I should use the dac_clk (loopback from the input tx_clk) from the ad9144_core as the clock source for my encoder, and adc_clk (loopback from the input rx_clk) from ad9680_core as the clock source to my decoder. And which signal should I use as the trigger for my custom IP? dac_enable is set when dma data is selected. Can I use this signal just to trigger my encoder and let it sent data to ad9144_core? I am little bit confused of the difference between dac_enable and dac_valid.