In the ADI's 4.0.0 reference kernel  the delay needed for stmmac SW DMA reset has been increased:
The "limit" value has been increased from 10 to 1000. Why it was necessary to increase this delay by two orders of magnitude?
From my measurements it turns out that one needs around 250 x 10ms loops to get the DMA SW reset to complete......
This is a lot..... when you strive for reducing boot time.
Is there any way to reduce this time?
I'm using ADSP-SC584 SoC embedded on LPC-EZBOARD (ezkit-lpc)
Thanks in advance for explanation,