Hi! Any design advice on using Xilinx AXI qaud SPI to control AD9361?
In Zcu102 example design, the PS SPI is used. Now the PL SPI will be used.
I am a new bee. Please help!
The KC705 reference design uses the Xilinx Quad SPI for SPI communication with the AD9361. Maybe you can use that as an example and adopt it your platform
Have a look at hdl/kc705_system_bd.tcl at dev · analogdevicesinc/hdl · GitHub and hdl/projects/fmcomms2/kc705 at dev · analogdevicesinc/hdl · GitHub
Moved to FPGA reference designs.
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