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FMC DAQ2 max frequency

Question asked by cerasic on Jun 12, 2017
Latest reply on Jun 12, 2017 by CsomI



I have a question about the data rate on the ADC to DRAM path (AD-FMCDAQ2-EBZ HDL Reference Design [Analog Devices Wiki] ), at DDR/BRAM fifo output  (64 bit @ 100 Mhz  )  means that  4 samples @ 100 Mz, does that mean the maximum signal we can synthetize and sample with ADC  200 Mhz Bandwidth (half nyquist 400 Mhz) ..  or did  I have misunderstanstood, something ?