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ADV7391 VIdeo DAC output not showing up

Question asked by Preetu@17 on Jun 10, 2017
Latest reply on Aug 22, 2017 by Anthony_Purcell



I am working on a project which has two decodes ADV7180 and and the outputs goes to FPGA. From the FPGA then it goes to encoder ADV7391, I am able to track the inputs(decoder) and outputs(fpga) until the encoder inputs(FPGA inputs, but the DAC  output there is no waveform .Also only DAC 1 and DAC 2 is there in my design schematic. There is no DAC3

The clock is 28.6363

I have set all the registers using the I2C bus

one of the decode and the other decoder with address as 0x42

/* TX Slv Sub */

/* Cnt Addr Addr data */

//{0x02, 0x40, 0x11, 0x1E}, /*48 PIN*/

//{0x02, 0x40, 0x13, 0x04}, /* disable the voltage output on the XTAL1 pin and allow the ADV7180 to be clocked by a 28.63636 MHz oscillator */

{0x02, 0x40, 0x00, 0x00},

{0x02, 0x40, 0x14, 0x30}, /* ADI required write (after any INSEL write) reset clamp circuitry */

{0x02, 0x40, 0x04, 0x57}, /* enable SFL output */

{0x02, 0x40, 0x17, 0x41}, /* select SH1 chroma shaping filter */

{0x02, 0x40, 0x31, 0x02}, /* enable NEWAVMODE */

{0x02, 0x40, 0x3D, 0xA2}, /* ADI required write (optimize windowing function step 1) */

{0x02, 0x40, 0x3E, 0x6A}, /* ADI required write (optimize windowing function step 2) */

{0x02, 0x40, 0x3F, 0xA0}, /* ADI required write (optimize windowing function step 3) */

{0x02, 0x40, 0x0E, 0x80}, /* ADI required write (enable ADC step 1) */

{0x02, 0x40, 0x55, 0x81}, /* ADI required write (enable ADC step 2) */

{0x02, 0x40, 0x0E, 0x00}, /* ADI required write (enable ADC step 3) */

{0x02, 0x40, 0x52, 0x0D} /* recommended AFE Ibias setting for CVBS mode */




encoder register settings

/* Cnt Addr Addr data */

{0x02, 0x54, 0x17, 0x02},

{0x02, 0x54, 0x00, 0x12},

{0x02, 0x54, 0x01, 0x00},

{0x02, 0x54, 0x02, 0x60},

{0x02, 0x54, 0x80, 0x10},

{0x02, 0x54, 0x82, 0xC9},

{0x02, 0x54, 0x84, 0x4E},

{0x02, 0x54, 0x87, 0x20},

{0x02, 0x54, 0x88, 0x00},

{0x02, 0x54, 0x8A, 0x0C}



Please suggest if the register settings are fine