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AD7266 use different SCLK and get different AD_DAT

Question asked by heshuangwang@sina.com on Jun 10, 2017
Latest reply on Jun 19, 2017 by jcolao

Hello,I am using AD7266 to communicate FPGA;

AVDD and DVDD +5V   Vdrive +3.3V   RANGE = 3.3V   REF_SEL = LOW (use inter REF)   SGL = ON

when i use 8MHz_SCLK  and got the corrent AD result data;

but when i use 16MHz_SCLK and got a wrong data,Data appears to be drifting considerably.

t2 and t9 are enough..

 

just like pictures below:

1.Vin=+2.5VSCLK-8MHz,AD_dat1111 1111 1111B = 0xFFF = 4095

BUT 

2. Vin=+2.5VSCLK-16MHz,采样结果:1111 1011 0101B = 0xFB5 = 4021   (WRONG)

 

I WANT TO KNOW WHY?

 

THANKS

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