I use ADIsimPLL4.2 to predict the PLL phase noise.
Of course, the phase noise simulation result of the PLL varies depending on the phase noise of the reference clock. I wonder how it is most reliable to set it.
What should I choose from the Phase noise option (Point / Floor or corner / Floor) in ADIsimPLL4.2?
The phase noise of TCXO is attached. Which value should be reflected in ADIsimPLL4.2?