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FMCOMMS2 ADC output delay

Question asked by tao.yu Employee on Jun 9, 2017
Latest reply on Jun 13, 2017 by CsomI



I have recently been evaluating FMCOMMS2 for a project and have trouble figuring out some of the timing specs of the HDL blocks used in the Vivado project on the Github. Specifically, I am wondering what is the timing relation between the output of the axi_ad9361 IP (adc_data_i0, adc_data_q0, adc_data_i1, adc_data_q1) with repsect to the LVDS input? Since the l_clk is derived from the LVDS clock, how many clock cycles is adc_data_i0 delayed from the LVDS input (rising edge of rx_frame_p)?