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AD9914 reference clock multiples setting

Question asked by waderose on Jun 9, 2017
Latest reply on Jun 20, 2017 by mcee

The manual says:"set the PLL feedback divider.". The frequency divider range is from 8 x to 255 x .Bits [15:8] = 0000 = 8 x, 0001 = 9 x... ,1111 = 255 x.But obviously 8 bits, how did they only write 4 bits? Seek explanation........

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