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FSCOMMS2 ADC output delay and TX_MON path

Question asked by tao.yu Employee on Jun 8, 2017
Latest reply on Sep 8, 2017 by sripad



I have recently been evaluating FSCOMMS2 for a project and have trouble figuring out some of the timing specs of the HDL blocks used in the Vivado project on the Github. Specifically, I am wondering what is the timing relation between the output of the axi_ad9361 IP (adc_data_i0, adc_data_q0, adc_data_i1, adc_data_q1) with repsect to the LVDS input? Since the l_clk is derived from the LVDS clock, is adc_data_i0 going to be 1  or 2 clock cycles delayed from the LVDS input (rising edge of rx_frame_p)?


My second question is about the TX_MON path. I am trying to get the TPM Test Mode working. So I can receive I/Q data at the RX output. How should I do that? Which RX port is it going to use?